1. Field of the Invention
The present invention relates to a monostable multivibrator circuit, and more specifically to a re-triggerable monostable multivibrator including a time constant circuit having at least a capacitor and for generating a predetermined width of pulse.
2. Description of Related Art
Referring to FIG. 1, there is shown one typical conventional timing generation circuit which forms an essential part of a monostable multivibrator. The shown timing generation circuit includes a first emitter coupled differential logic circuit ECL1, which comprises a transistor Q.sub.1 having a base connected to an input IN and a collector connected to a ground line GND, another transistor Q.sub.2 having a base connected to receive a reference voltage V.sub.ref and a collector connected through a resistor R.sub.1 to the ground line GND, and a constant current source I.sub.cs1 connected between commonly connected emitters of the transistors Q.sub.1 and Q.sub.2 and a negative voltage line V.sub.EE. The collector of the transistor Q.sub.2, which forms a non-inverted output of the emitter coupled differential logic circuit ECL1, is connected to a base of a third transistor Q.sub.3, which has a collector connected to the ground line GND.
Furthermore, the shown timing generation circuit includes a time constant circuit composed of a capacitor C and a constant current source I.sub.0 series-connected between the ground line GND and the negative voltage line V.sub.EE. A connection node X between the capacitor C and the constant current source I.sub.0 is connected to an emitter of the transistor Q.sub.3. Thus, the transistor Q.sub.3 forms an emitter follower.
The node X of the time constant circuit is connected to an input of a second emitter coupled differential logic circuit ECL21, which comprises a transistor Q.sub.4 having a base connected to the node X and a collector connected through a resistor R.sub.2 to the ground line GND, another transistor Q.sub.5 having a base connected to receive a reference voltage V.sub.ref1 slightly higher than a low level potential and a collector connected to the ground line GND, and a constant current source I.sub.cs2 connected between commonly connected emitters of the transistors Q.sub.4 and Q.sub.5 and the negative voltage line V.sub.EE. The collector of the transistor Q.sub.4, which forms an inverted output of the second emitter coupled differential logic circuit ECL2, is connected to a base of a transistor Q.sub.6, which has a collector connected to the ground line GND and an emitter connected through a resistor R.sub.3 to the negative voltage line V.sub.EE. The emitter of the transistor Q.sub.6 is connected to an output OUT1. Thus, the transistor Q.sub.6 forms an emitter follower.
The above mentioned timing generation circuit operates as follows:
As seen from the above, since the first emitter coupled differential logic circuit ECL1 outputs a signal in phase with an input signal, a signal applied to the input IN is a high level, the node X is brought a high level. At this time, a potential of the node X is substantially equal to a potential which is lower than a ground level of the ground line GND by a forward direction base-emitter voltage V.sub.BE of the transistor Q.sub.3 when a constant current I.sub.0 flows through the transistor Q.sub.3.
On the other hand, the second emitter coupled differential logic circuit ECL2 generates an output signal in a reverse phase to an input signal applied to the second emitter coupled differential logic circuit ECL2, and therefore, a signal appearing at the node X is converted into an opposite phase signal. Namely, when the node X is at a high level, the output OUT1 is brought to a low level.
Now, assuming that the input signal on the input terminal IN is brought from the high level to a low level, a voltage drop V will occur across the resistor R.sub.1 {V=R.sub.1 .multidot.I.sub.cs1 }, so that the emitter follower transistor Q.sub.3 is cut off, with the result that the constant current source I.sub.0 will start to charge the capacitor C.
Referring to FIG. 2, there is shown a timing chart illustrating an operation of the timing generation circuit shown in FIG. 1. A left half of FIG. 2 shows a condition in which the charging of the capacitor C is started as mentioned above and then the potential of the node X is gradually lowered at a constant rate which is determined by the time constant of the time constant circuit.
When the potential of the node X becomes lower than the first reference voltage V.sub.ref1 which is applied as the reference potential for the second emitter coupled differential logic circuit ECL2, the output of this second emitter coupled differential logic circuit ECL2 is inverted from the low level to the high level.
Here, a time length T.sub.1 starting from a transition of the input signal IN from the high level to the low level and terminating at a transition of the output signal OUT1 from the low level to the high level, can be expressed as follows:
First, the amount of electric charge Q stored in the capacitor C is expressed: EQU Q=C.multidot..vertline.V.sub.ref1 -V.sub.BE .vertline.
Therefore, ##EQU1## Furthermore, if the low level of the input signal IN is continuously maintained as it is, the potential of the node X is stabilized at the low level after a time length T.sub.2 has been elapsed. The time length T.sub.2 can be expressed as follows: ##EQU2## Namely, the potential of the node X becomes at a level which is lower than the ground level by R.sub.1 .multidot.I.sub.cs1 +V.sub.BE. If the input signal is returned to the high level before the time T.sub.1 elapses, the output signal OUT1 will not change its level, and therefore, is maintained at the low level.
On the other hand, when the input signal IN changes from the low level to the high level, the electric charge stored in the capacitor C will discharge through the transistor Q.sub.3 at a time length which is considerably shorter than the charging time.
In the above mentioned timing generation circuit for the monostable multivibrator, when the input signal IN is brought from the high level to the low level, the transistor Q.sub.3 is cut off, so that the charging of the capacitor C is started. In some case, however, the input signal is brought from high level to the low level in the course of the discharging of the capacitor C, namely, in the process in which the potential of the node X is changing from the low level toward the high level. In this case, the charging of the capacitor C is restarted before the electric charge of the capacitor C has been completely discharged.
Referring to a right hand of FIG. 2, there is illustrated the above mentioned situation. In this case, since the discharge of the capacitor C is not sufficient, the time T from the moment the input signal changes from the high level to the low level to the moment the output signal changes from the low level to the high level, is smaller than the above mentioned time length T.sub.1. In other words, it is not possible to ensure the predetermined response time T.sub.1 after the leading edge of the input signal IN until the tail edge of the output signal OUT1.
Referring to FIG. 3, there is shown a conventional monostable multivibrator which incorporates therein the timing generation circuit shown in FIG. 1. In FIG. 3, the timing generation circuit shown in FIG. 1 is given the reference numeral 1.
The monostable multivibrator shown in FIG. 3 includes a D-type flipflop 2, which has a data input D connected to a high level "H" and a clock input CK connected to a clock terminal CLOCK. A Q output of the flipflop 2 is connected to a node A, which is connected to one input of an OR gate 5. An output of the OR gate 5 is connected to the input IN of the timing generation circuit 1. The node A is also connected to an input of another OR gate 6, which has an output connected to a reset input RESET of the flipflop 2. The other input of the OR gate 6 is connected to a clear terminal CLEAR. A Q output of the flipflop 2 is connected to one input of a NOR gate 7, which has the other input connected to the clear terminal CLEAR.
The output OUT1 of the timing generation circuit 1 is connected to a clock input CK of another D-type flipflop 8. This D-type flipflop 8 has a data input D connected to a low level "L", and a Q output connected to an output terminal OUT of the multivibrator. The D-type flipflop 8 also has a set input SET connected to an output of the NOR gate 7, and a reset input RESET connected to the clear terminal CLEAR. In addition, a Q output of the flipflop 8 is connected to the other input of the OR gate 5.
Now, an operation of the monostable multivibrator shown in FIG. 3 will be described with reference to FIG. 4.
First, a high level signal is applied to the clear terminal CLEAR so as to initialize the circuit. As a result, the following initialized condition is established:
Node A=low level PA0 Output terminal OUT=low level PA0 Input IN of the timing generation=high level PA0 Node X of the timing generation=high level PA0 Output OUT1 of the timing generation=low level
After the clear signal is cancelled or brought to a low level, a trigger signal is applied to the clock input CLOCK. With the change of the signal inputted to the clock terminal CLOCK from the low level to the high level, the Q output of the flipflop 2 will change from the low level to the high level and further immediately change to the low level, since the Q output of the flipflop 2 is fed back to the reset terminal RESET of the flipflop 2 through the OR gate 6, so that the Q output of the flipflop 2 generates a narrow width of pulse as shown in FIG. 4. Simultaneously, the Q output of the flipflop 2 generates a negative-going narrow pulse, which is inputted through the NOR gage 7 to the set input SET of the flipflop 8, so that the output terminal OUT of the multivibrator is brought to a high level, and on the other hand, the input IN of the timing generation circuit 1 is brought to a low level. From this moment, the constant current source I.sub.0 starts the charging of the capacitor C in the time constant circuit.
The potential of the node X will drop with time, and when the potential of the node X reaches to the reference voltage V.sub.ref1, the output OUT1 of the timing generation circuit 1 is changed from the low level to the high level, so that the flipflop 8 is caused to change its state. Specifically, the output terminal OUT is brought to a low level, and the input IN of the timing generation circuit 1 is brought to the high level, so that the capacitor C of the time constant circuit will start its discharge.
A left half of the timing chart shown in FIG. 4 illustrates the above mentioned operation. The time length T.sub.1 of the high level of the output pulse appearing on the terminal OUT is determined by the time constant of the constant current source I.sub.0 and the capacitor C.
A right half of FIG. 4 illustrates a situation in which a trigger signal is applied again to the clock terminal CLOCK in the way of the discharging of the capacitor C, namely before the time period T.sub.1 for outputting the high level signal to the output terminal OUT elapses. In the monostable multivibrator shown in FIG. 3, the narrow width positive-going pulse generated at the node A by the re-trigger signal will function to discharge the capacitor C. In the case that the capacitor C has a relative large capacitance, the charging is restarted before the discharge of the capacitor C has been completed. As a result, the time length T from the application of the re-trigger signal until the output terminal OUT is changed from the high level to the low level is smaller than the predetermined time T.sub.1, since the charge of the capacitor C has not been completely discharged at once.